View AN87C196LB_3260154.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

intel corporation assumes no respon sibility for the use of any circuitry other than circuitry embodied in an intel product. no other circuit patent licenses are implied. information contained herein supersedes previously published specifications on these devices from intel. ? intel corporation, 1996 february 1996 order number: 272807-000 ? pr oduct preview 87c196lb chmos 16-bit microcontroller automotive note this datasheet contains information on products in the design phase of development. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design. the 87c196lb is a high-performance 16-bit microcontroller with integrated support for the j1850 communication protocol. the 87c196lb is composed of a high-speed core with the following peripherals: an asynchronous/synchronous serial i/o port (8096 compatible) with a dedicated 16-bit baud -rate generator; an additional synchronous serial i/o port with full duplex master/slave transceivers; a six-channel a/d converter with sample and hold; a flexible timer/counter structure with prescaler, cascading, and quadrature capabilities; six modularized, multiplexed high-speed i/o for capture and compare (called event processor array) with 200 ns resolution and double buffered inputs; and a sophisticated prioritized interrupt structure with programmable peripheral transaction server (pts). the clock doubler circuitry and oscillator output signal enable a 4 mhz resonator to achieve the same internal clock speed as a more costly 8 mhz resonator in previous applications. this same circuitry can drive other devices where a separate resonator was required in the past. another cost- savings feature is the fact that the i/o ports are driven low at reset, avoiding the need for pull-up resistors. n 20 mhz operation ? n 24 kbytes of on-chip otprom n 768 bytes of on-chip register ram n register-to-register architecture n peripheral transaction server (pts) with high-speed, microcoded interrupt service routines n integrated, industry-standard j1850 communication protocol n six-channel/10-bit a/d with sample and hold n high-speed event processor array six capture/compare channels two compare-only channels two 16-bit software timers ? 16 mhz standard; 20 mhz is speed premium n full-duplex serial i/o port with dedicated baud-rate generator n enhanced full-duplex, synchronous serial i/o port (ssio) n programmable 8- or 16-bit external bus n optional clock doubler with programmable clock output signal n sfr register that indicates the source of the last reset n design enhancements for emi reduction n oscillator failure detection circuitry n watchdog timer (wdt) n C 40 c to + 125 c ambient temperature n 52-pin plcc package
pr oduct preview 2 automotive ? figure 1. 87c196lb block diagram queue source (16) destination (16) ad15:0 epa 2 timers 6 capture/ compare channels ? bus controller watchdog timer enhanced ssio otprom 24 kbytes a3416-01 sio baud-rate generator port 6 memory data bus (16) bus-control interface unit microcode engine peripheral transaction server memory interface unit register ram 768 bytes alu interrupt controller bus control peripheral addr bus (10) peripheral data bus (16) memory addr bus (16) 2 compare-only channels port 2 port 1,6 port 0 a/d converter j1850 protocol handler ? two additional capture/compare channels (epa6 and epa7) are available as software timers. port 2 they are not connected to package pins.
3 automotive ? pr oduct preview 1.0 nomenclature overview figure 2. product nomenclature table 1. description of product nomenclature parameter options description temperature and burn-in options a automotive operating temperature range (C40 c to 125 c ambient) with intel standard burn-in. packaging options n plcc program-memory options 7 otprom process information c chmos product family 196l x 8xc196l x family of products device speed no mark 20 16 mhz 20 mhz program-memory options xxxxx xx x x 8 xx x packaging options temperature and burn-in options a2815-02 process and voltage information product family device speed
pr oduct preview 4 automotive ? 2.0 pinout figure 3. 87c196lb 52-pin package p6.1 / epa9 / comp1 p6.0 / epa8 / comp0 p1.0 / epa0 / t2clk p1.1 / epa1 p1.2 / epa2 / t2dir p1.3 / epa3 v ref angnd p0.7 / ach7 / pmode.3 p0.6 / ach6 / pmode.2 p0.5 / ach5 / pmode.1 p0.4 / ach4 / pmode.0 p0.3 / ach3 ad15 / p4.7 / pbus.15 p5.2 / pllen /wr# / wrl# p5.3 / rd# v pp v ss (core) p5.0 / adv# / ale v ss1 (port) xtal1 xtal2 p6.7 / sd1 p6.6 / sc1 p6.5 / sd0 p6.4 / sc0 a3361-01 ad14 / p4.6 / pbus.14 ad13 / p4.5 / pbus.13 ad12 / p4.4 / pbus.12 ad11 / p4.3 / pbus.11 ad10 / p4.2 / pbus.10 ad9 / p4.1 / pbus.9 ad8 / p4.0 / pbus.8 ad7 / p3.7 / pbus.7 ad6 / p3.6 / pbus.6 ad5 / p3.5 / pbus.5 ad4 / p3.4 / pbus.4 ad3 / p3.3 / pbus.3 ad2 / p3.2 / pbus.2 46 45 44 43 42 41 40 39 38 37 36 35 34 AN87C196LB view of component as mounted on pc board 8 9 10 11 12 13 14 15 16 17 18 19 20 ad1 / p3.1 / pbus.1 ad0 / p3.0 / pbus.0 reset# ea# v ss1 (port) v cc p2.0 / txd / pver p2.1 / rxd / pale# p2.2 / extint / prog# p2.4 / rxj1850 / ainc# p2.6/txj1850 / cpver p2.7 / clkout / pact# p0.2 / ach2 21 22 23 24 25 26 27 28 29 30 31 32 33 7 6 5 4 3 2 1 52 51 50 49 48 47
5 automotive ? pr oduct preview table 2. 87c196lb 52-pin package pin assignments pin name pin name pin name 1v ss 1 (port) 19 ad3 / p3.3 / pbus.3 37 p0.6 / ach6 / pmode.2 2 p5.0 / adv# / ale 20 ad2 / p3.2 / pbus.2 38 p0.7 / ach7 / pmode.3 3v ss (core) 21 ad1 / p3.1 / pbus.1 39 a ngnd 4v pp 22 ad0 / p3.0 / pbus.0 40 v ref 5 p5.3 / rd# 23 reset# 41 p1.3 / epa3 6 p5.2 / pllen / wr# / wrl# 24 ea# 42 p1.2 / epa2 / t2dir 7 ad15 / p4.7 / pbus.15 25 v ss 1 (port) 43 p1.1 / epa1 8 ad14 / p4.6 / pbus.14 26 v cc 44 p1.0 / epa0 / t2clk 9 ad13 / p4.5 / pbus.13 27 p2.0 / txd / pver 45 p6.0 / epa8 / comp0 10 ad12 / p4.4 / pbus.12 28 p2.1 / rxd / pale# 46 p6.1 / epa9 / comp1 11 ad11 / p4.3 / pbus.11 29 p2.2 / extint / prog# 47 p6.4 / sc0 12 ad10 / p4.2 / pbus.10 30 p2.4 / rxj1850 / ainc# 48 p6.5 / sd0 13 ad9 / p4.1 / pbus.9 31 p2.6 / txj1850 / cpver 49 p6.6 / sc1 14 ad8 / p4.0 / pbus.8 32 p2.7 / clkout / pact# 50 p6.7 / sd1 15 ad7 / p3.7 / pbus.7 33 p0.2 / ach2 51 xtal2 16 ad6 / p3.6 / pbus.6 34 p0.3 / ach3 52 xtal1 17 ad5 / p3.5 / pbus.5 35 p0.4 / ach4 / pmode.0 18 ad4 / p3.4 / pbus.4 36 p0.5 / ach5 / pmode.1
pr oduct preview 6 automotive ? table 3. pin assignment arranged by functional categories addr & data input/output (contd) program control processor control name pin name pin name pin name pin ad0 22 p2.1 / rxd 28 ainc# 30 ea# 24 ad1 21 p2.2 29 cpver 31 extint 29 ad2 20 p2.4 / rxj1850 30 pact# 32 pllen 6 ad3 19 p2.6 / txj1850 31 pale# 28 reset# 23 ad4 18 p2.7 32 pbus.0 22 xtal1 52 ad5 17 p3.0 22 pbus.1 21 xtal2 51 ad6 16 p3.1 21 pbus.2 20 ad7 15 p3.2 20 pbus.3 19 bus cont & status ad8 14 p3.3 19 pbus.4 18 name pin ad9 13 p3.4 18 pbus.5 17 adv# / ale 2 ad10 12 p3.5 17 pbus.6 16 clkout 32 ad11 11 p3.6 16 pbus.7 15 rd# 5 ad12 10 p3.7 15 pbus.8 14 wr# / wrl# 6 ad13 9 p4.0 14 pbus.9 13 ad14 8 p4.1 13 pbus.10 12 power & ground ad15 7 p4.2 12 pbus.11 11 name pin p4.3 11 pbus.12 10 angnd 39 input/output p4.4 10 pbus.13 9 v cc 26 name pin p4.5 9 pbus.14 8 v pp 4 p0.2 / ach2 33 p4.6 8 pbus.15 7 v ref 40 p0.3 / ach3 34 p4.7 7 pmode.0 35 v ss (core) 3 p0.4 / ach4 35 p5.0 2 pmode.1 36 v ss 1 (port) 1, 25 p0.5 / ach5 36 p5.2 6 pmode.2 37 p0.6 / ach6 37 p5.3 5 pmode.3 38 p0.7 / ach7 38 p6.0 / epa8 / comp0 45 prog# 29 p1.0 / epa0 / t2clk 44 p6.1 / epa9 / comp1 46 pver 27 p1.1 / epa1 43 p6.4 / sc0 47 p1.2 / epa2 / t2dir 42 p6.5 / sd0 48 p1.3 / epa3 41 p6.6 / sc1 49 p2.0 / txd 27 p6.7 / sd1 50
7 automotive ? pr oduct preview 3.0 signals table 4. signal descriptions name type description ach7:2 i analog channels these signals are analog inputs to the a/d converter. the a/d inputs share package pins with port 0. these pins may individually be used as analog inputs (ach x ) or digital inputs (p0. y ). while it is possible for the pins to function simultaneously as analog and digital inputs, this is not recommended because reading port 0 while a conversion is in process can produce unreliable conversion results. the angnd and v ref pins must be connected for the a/d converter and port 0 to function. ach7:2 share package pins with the following signals: ach2/p0.2, ach3/p0.3, ach4/p0.4/pmode.0, ach5/p0.5/pmode.1, ach6/p0.6/pmode.2, and ach7/p0.7/pmode.3. ad15:0 i/o address/data lines these pins provide a multiplexed address and data bus. during the address phase of the bus cycle, address bits 0C15 are presented on the bus and can be latched using ale or adv#. during the data phase, 8- or 16-bit data is transferred. ad7:0 share package pins with p3.7:0 and pbus.7:0; ad15:8 share package pins with p4.7:0 and pbus.15:8. adv# o address valid this active-low output signal is asserted only during external memory accesses. adv# indicates that valid address information is available on the system address/data bus. the signal remains low while a valid bus cycle is in progress and is returned high as soon as the bus cycle completes. an external latch can use this signal to demultiplex the address from the address/data bus. a decoder can also use this signal to generate chip selects for external memory. adv# shares a package pin with p5.0 and ale. ainc# i auto increment during slave programming, this active-low input enables the auto-increment feature. (auto increment allows reading or writing of sequential otprom locations, without requiring address transactions a cross the pbus for each read or write.) ainc# is sampled after each location is programmed or dumped. if ainc# is asserted, the address is incremented and the next data word is programmed or dumped. ainc# shares package pins with p2.4 and rxj1850. ale o address latch enable this active-high output signal is asserted only during external memory cycles. ale signals the start of an external bus cycle and indicates that valid address information is available on the system address/data bus. an external latch can use this signal to demultiplex the address from the address/data bus. ale shares a package pin with p5.0 and adv#.
pr oduct preview 8 automotive ? angnd gnd analog ground angnd must be connected for a/d converter and port 0 operation. angnd and v ss should be nominally at the same potential. clkout o output output of the internal clock generator. you can select one of three frequencies: f, f/2, or f/4. clkout has a 50% duty cycle. clkout shares a package pin with p2.7 and pact#. comp1:0 o event processor array (epa) compare pins these signals are the outputs of the epa compare-only channels. comp1:0 share package pins with the following signals: comp0/p6.0/epa8 and comp1/p6.1/epa9. cpver o cumulative program verification during slave programming, a high signal indicates that all locations programmed correctly, while a low signal indicates that an error occurred during one of the programming operations. cpver shares a package pin with p2.6, txj1850, and once#. ea# i external access this input determines whether memory accesses to special-purpose and program memory partitions are directed to internal or external memory. these accesses are directed to internal memory if ea# is held high and to external memory if ea# is held low. for an access to any other memory location, the value of ea# is irrelevant. ea# also controls entry into the programming modes. if ea# is at v pp voltage (typically +12.5 v) on the rising edge of reset#, the microcontroller enters a programming mode. note: systems with ea# tied inactive have idle time between external bus cycles. when the address/data bus is idle, you can use ports 3 and 4 for i/o. systems with ea# tied active cannot use ports 3 and 4 as standard i/o; when ea# is active, these ports will function only as the address/data bus. when ea# is active, a read or write to p3_reg, p4_reg, p3_pin, or p4_pin accesses the corresponding location (1ffch, 1ffdh, 1ffeh, or 1fffh) in external memory. ea# is sampled and latched only on the rising edge of reset#. changing the level of ea# after reset has no effect. epa9:8 epa3:0 i/o event processor array (epa) capture/compare channels high-speed input/output signals for the epa capture/compare channels. the epa signals share package pins with the following signals: epa0/p1.0/t2clk, epa1/p1.1, epa2/p1.2/t2dir, epa3/p1.3, epa8/p6.0/comp0, and epa9/p6.1/comp1. epa7:6 do not connect to package pins. they cannot be used to capture an event, but they can function as software timers. epa5:4 are not implemented. table 4. signal descriptions (continued) name type description
9 automotive ? pr oduct preview extint i external interrupt in normal operating mode, a rising edge on extint sets the extint interrupt pending bit. extint is sampled during phase 2. the minimum high time is one state time. in powerdown mode, asserting the extint signal for at least 50 ns causes the device to resume normal operation. the interrupt need not be enabled. if the extint interrupt is enabled, the cpu executes the interrupt service routine. otherwise, the cpu executes the instruction that immediately follows the command that invoked the power-saving mode. in idle mode, asserting any enabled interrupt causes the device to resume normal operation. extint shares a package pin with p2.2 and prog#. p0.7:2 i port 0 this is a high-impedance, input-only port. port 0 pins should not be left floating. the port 0 signals share package pins with the a/d inputs. these pins may individually be used as analog inputs (ach x ) or digital inputs (p0. y ). while it is possible for the pins to function simultaneously as analog and digital inputs, this is not recommended because reading port 0 while a conversion is in process can produce unreliable conversion results. angnd and v ref must be connected for port 0 to function. p0.3:2 share package pins with ach3:2 and p0.7:4 share package pins with ach7:4 and pmode.3:0. p1.3:0 i/o port 1 this is a standard bidirectional port that shares package pins with individually selectable special-function signals. port 1 shares package pins with the following signals: p1.0/epa0/t2clk, p1.1/epa1, p1.2/epa2/t2dir, p1.3/epa3. p2.7:6 p2.4 p2.2:0 i/o port 2 this is a standard bidirectional port that shares package pins with individually selectable special-function signals. port 2 shares package pins with the following signals: p2.0/txd/pver, p2.1/rxd/pale#, p2.2/extint/prog#, p2.4/ainc#/rxj1850, p2.6/txj1850/once#/cpver, p2.7/oscout/pact#. p3.7:0 i/o port 3 this is a memory-mapped, 8-bit, bidirectional port with programmable open- drain or complementary output modes. the pins are shared with the multiplexed address/data bus, which has complementary drivers.. p3.7:0 share package pins with ad7:0 and pbus.7:0. p4.7:0 i/o port 4 this is a memory-mapped, 8-bit, bidirectional port with open-drain or complementary output modes. the pins are shared with the multiplexed address/data bus, which has complementary drivers. p4.7:0 share package pins with ad15:8 and pbus.15:8. table 4. signal descriptions (continued) name type description
pr oduct preview 10 automotive ? p5.3:2 p5.0 i/o port 5 this is a memory-mapped, bidirectional port. port 5 shares package pins with the following signals: p5.0/adv#/ale, p5.2/wr#/wrl#/pllen, and p5.3/rd#. p5.1 and p5.7:4 are not implemented. p6.7:4 p6.1:0 o port 6 this is a standard bidirectional port. port 6 shares package pins with the following signals: p6.0/epa8/comp0, p6.1/epa9/comp1, p6.4/sc0, p6.5/sd0, p6.6/sc1, and p6.7/sd1. pact# o programming active during auto programming or rom-dump, a low signal indicates that programming or dumping is in progress, while a high signal indicates that the operation is complete. pact# is multiplexed with p2.7 and oscout. pale# i programming ale during slave programming, a falling edge causes the device to read a command and address from the pbus. pale# is multiplexed with p2.1 and rxd. pbus.15:0 i/o address/command/data bus during slave programming, ports 3 and 4 serve as a bidirectional port with open-drain outputs to pass comman ds, addresses, and data to or from the device. slave programming requires external pull-up resistors. during auto programming and rom-dump, ports 3 and 4 serve as a regular system bus to access external memory. p4.6 and p4.7 are left unconnected; p1.1 and p1.2 serve as the upper address lines. slave programming: pbus.7:0 share package pins with ad7:0 and p3.7:0. pbus.15:8 share package pins with ad15:8 and p4.7:0. auto programming: pbus.15:8 share package pins with ad15:8 and p4.7:0; pbus.7:0 share package pins with ad7:0 and p3.7:0. pllen i phase-locked loop enable this active-high input pin enables the on-chip clock multiplier. pmode.3:0 i programming mode select determines the programming mode. pmode is sampled after a device reset and must be static while the microcontroller is operating. pmode.3:0 are multiplexed with p0.7:4 and ach7:4. table 4. signal descriptions (continued) name type description
11 automotive ? pr oduct preview prog# i programming s tart during programming, a falling edge latches data on the pbus and begins programming, while a rising edge ends programming. the current location is programmed with the same data as long as prog# remains asserted, so the data on the pbus must remain stable while prog# is active. during a word dump, a falling edge causes the contents of an otprom location to be output on the pbus, while a rising edge ends the data transfer. prog# is multiplexed with p2.2 and extint. pver o program verification during slave or auto programming, pver is updated after each programming pulse. a high output signal indicates successful programming of a lo cation, while a low signal indicates a detected error. pver is multiplexed with p2.0 and txd. rd# o read read-signal output to external memory. rd# is asserted only during external memory reads. rd# shares a package pin with p5.3. reset# i/o reset a level-sensitive reset input to and open-drain system reset output from the microcontroller. either a falling edge on reset# or an internal reset turns on a pull-down transistor connected to the reset# pin for 16 state times. in the powerdown and idle modes, asserting reset# causes the chip to reset and return to normal operating mode. after a device reset, the first instruction fetch is from 2080h. rxj1850 i receive this signal carries messages from an off-chip, j1850 transceiver to the integrated j1850 module. rxj1850 shares a package pin with p2.4 and ainc#. rxd i/o receive serial data in modes 1, 2, and 3, rxd receives serial port input data. in mode 0, it functions as either an input or an open-drain output for data. rxd shares a package pin with p2.1 and pale#. sc1:0 i/o clock pins for ssio0 and 1 for handshaking mode, configure sc1:0 as open-drain outputs. this pin carries a signal only during receptions and transmissions. when the ssio port is idle, the pin remains either high (with handshaking) or low (without handshaking). sc0 shares a package pin with p6.4, and sc1 shares a package pin with p6.6. sd1:0 i/o data pins for ssio0 and 1 these pins are the data i/o pins for ssio0 and 1. sd0 shares a package pin with p6.5, and sd1 shares a package pin with p6.7. table 4. signal descriptions (continued) name type description
pr oduct preview 12 automotive ? t2clk i timer 2 external clock external clock for timer 2. timer 2 increments (or decrements) on both rising and falling edges of t2clk. it is also used in conjunction with t2dir for quadrature counting mode. t2clk shares a package pin with p1.0 and epa0. t2dir i timer 2 external direction external direction (up/down) for timer 2. timer 2 increments when t2dir is high and decrements when it is low. it is also used in conjunction with t2clk for quadrature counting mode. t2dir shares a package pin with p1.2 and epa2. txj1850 o transmit this signal carries messages from the integrated j1850 module to an off-chip j1850 transceiver. txj1850 must not be driven high during reset and should only be used as an output. txj1850 shares a package pin with p2.6, once#, and cpver. txd o transmit serial data in serial i/o modes 1, 2, and 3, txd transmits serial port output data. in mode 0, it is the serial clock output. txd shares a package pin with p2.0 and pver. v cc pwr digital supply voltage connect each v cc pin to the digital supply voltage. v pp pwr programming voltage v pp causes the device to exit powerdown mode when it is driven low for at least 50 ns. use this method to exit powerdown only when using an external clock source because it enables the internal phase clocks, but not the internal oscillator. if you do not plan to use the powerdown feature, connect v pp to v cc . v ref pwr reference voltage for the a/d converter this pin supplies operating voltage to the a/d converter. v ss , v ss 1 gnd digital circuit ground (core ground, port ground) these pins supply ground for the digital circuitry. connect each v ss and v ss 1 pin to ground through the lowest possible impedance path. v ss pins are con- nected to the core ground region of the microcontroller, while v ss 1 pins are con- nected to the port ground region. ( angnd is connected to the analog ground region.) separating the ground regions provides noise isolation. table 4. signal descriptions (continued) name type description
13 automotive ? pr oduct preview wr# o write ? this active-low output indicates that an external write is occurring. this signal is asserted only during external memory writes. forcing wr# high while reset# is low, causes the device to enter pll-bypass mode. when the device is in pll-bypass mode, the internal phase clocks operate at one-half the frequency of the frequency on xtal1. wr# shares a package pin with p5.2, wrl#, and pllen. ? the chip configuration register 0 (ccr0) determines whether this pin functions as wr# or wrl#. ccr0.2 = 1 selects wr#; ccr0.2 = 0 selects wrl#. wrl# o write low ? during 16-bit bus cycles, this active-low output signal is asserted for low-byte writes and word writes to external memory. during 8-bit bus cycles, wrl# is asserted for all write operations. wrl# shares package pin with p5.2, wr#, and pllen. ? the chip configuration register 0 (ccr0) determines whether this pin functions as wr# or wrl#. ccr0.2 = 1 selects wr#; ccr0.2 = 0 selects wrl#. xtal1 i input crystal/resonator or external clock input input to the on-chip oscillator and the internal clock generators. the internal clock generators provide the peripheral clocks, cpu clock, and clkout signal. when using an external clock source instead of the on-chip oscillator, connect the clock input to xtal1. the external clock signal must meet the v ih specification for xtal1. xtal2 o inverted output for the crystal/ resonator output of the on-chip oscillator inverter. leave xtal2 floating when the design uses an external clock source instead of the on-chip oscillator. table 4. signal descriptions (continued) name type description
pr oduct preview 14 automotive ? 4.0 address map 5.0 electrical characteristics table 5. address map hex address range description addressing modes ffff 8000 external device (memory or i/o) connected to address/data bus indirect or indexed 7fff 2080 program memory (internal nonvolatile or external memory); see note 1 indirect or indexed 207f 2000 special-purpose memory (internal nonvolatile or external memory) indirect or indexed 1fff 1fe0 memory-mapped sfrs indirect or indexed 1fdf 1f00 peripheral sfrs indirect, indexed, or windowed direct 1eff 0300 external device (memory or i/o) connected to address/data bus; (future sfr expansion; see note 2) indirect or indexed 02ff 0100 upper register file (general-purpose register ram) indirect, indexed, or windowed direct 00ff 0000 lower register file (register ram, stack pointer, and cpu sfrs) direct, indirect, or indexed notes: 1. after a reset, the microcontroller fetches its first instruction from 2080h. 2. the content or function of these locations may change in future microcontroller revisions, in which case a program that relies on a location in this range might not function properly. absolute maximum ratings storage temperature .................................. C60c to +150 c voltage from v pp or ea# to v ss or angnd... C 0.5v to +13.0 v voltage from any other pin to v ss or angnd ... C0.5v to +7.0v power dissi pation .......................................................... 0.5 w operating conditions ? t a (ambient temperature under bias)...........C40c to +125c v cc (digital supply voltage) ............................ 4.50v to 5.50v v ref (analog supply voltage)............................ 4.50v to 5.50v f xtal 1 (input frequency): - pll in 2x mode............................ 4 mhz to 10 mhz - pll in 1x mode............................ 8 mhz to 20 mhz notes 1. angnd and v ss should be nominally at the same potential. 2. v ref should not exceed v cc by more than 0.5v. notice: this document contains information on products in the design phase of develop- ment. do not finalize a design with this infor- mation. revised information will be published when the product is available. verify with your local intel sales office that you have the latest datasheet before finalizing a design. ? warning : stressing the device beyond the absolute maximum ratings may cause per- manent damage. these are stress ratings only. operation beyond the operating condi- tions is not recommended and extended exposure beyond the operating conditions may affect device reliability.
15 automotive ? pr oduct preview 5.1 dc characteristics table 6. dc characteristics at v cc = 4.5v to 5.5v symbol parameter min typical max units test conditions (note 4) i cc v cc supply current ( C 40 c to +125 c ambient) 50 tbd ma f xtal 1 = 20 mhz, v cc = v pp = v ref = 5.5v (while device is in reset) i cc 1 active mode supply cur- rent (typical) 50 ma i ref a/d reference supply current 2tbdma i idle idle mode current 15 tbd ma f xtal 1 = 20 mhz, v cc = v pp = v ref = 5.5v i pd powerdown mode current 50 tbd a v cc = v pp = v ref = 5.5v (note 6) v il input low voltage (all pins) C 0.5v 0.3 v cc v v ih input high voltage (all pins) 0.7 v cc v cc + 0.5 v (note 7) v ol output low voltage (outputs configured as complementary) 0.3 0.45 1.5 v v v i ol = 200 a (notes 3, 5) i ol = 3.2 ma i ol = 7.0 ma v oh output high voltage (outputs configured as complementary) v cc C 0.3 v cc C 0.7 v cc C 1.5 v v v i oh = C 200 a (notes 3, 5) i oh = C 3.2 ma i oh = C 7.0 ma i li input leakage current (standard inputs) 8 a v ss v in v cc (note 2) i li 1 input leakage current (port 0a/d inputs) 1 a v ss v in v ref i ih input high current (nmi pin, bond pao only) +175 a v ss v in v cc v ol 2 output low voltage in reset 1vi ol = 6 a (notes 1, 8) notes: 1. all bidirectional pins except p5.1/inst and p2.7/clkout which are excluded because they are not weakly pulled low in reset. bidirectional pins include ports 1C6. 2. standard input pins include xtal1, ea#, reset#, and ports 1C6 when configured as inputs. 3. all bidirectional pins when configured as complementary outputs. 4. device is static and should operate below 1 hz, but is only tested down to 4 mhz with the pll enabled. with the pll bypassed, the device is only tested down to 8mhz. 5. maximum i ol or i oh currents per pin will be characterized and published at a later date. target values are 10 ma. 6. typicals are based on a limited number of samples and are not guaranteed. the values listed are at room temperature and v ref = v cc = 5.5v. 7. v ih max for port 0 is v ref + 0.5v. 8. this specification is not tested in production and is based upon theoretical estimates and/or product characterization.
pr oduct preview 16 automotive ? i ol 2 output low current in reset tbd tbd tbd tbd tbd tbd a a a v ol 2 = tbd v ol 2 = tbd v ol 2 = tbd r rst reset pullup resistor 6k 65k w v ol 3 output low voltage in reset (reset# pin only) 0.3 0.5 0.8 v v v i ol 3 = 4 ma (note 8) i ol 3 = 6 ma i ol 3 = 10 ma v ol 4 output low voltage in reset (p2.6 only) 1vi ol 4 = tbd c s pin capacitance (any pin to v ss ) 10 pf f test = 1.0 mhz r wpu weak pullup resistance (approximate) 150k w (note 6) table 6. dc characteristics at v cc = 4.5v to 5.5v (continued) symbol parameter min typical max units test conditions (note 4) notes: 1. all bidirectional pins except p5.1/inst and p2.7/clkout which are excluded because they are not weakly pulled low in reset. bidirectional pins include ports 1C6. 2. standard input pins include xtal1, ea#, reset#, and ports 1C6 when configured as inputs. 3. all bidirectional pins when configured as complementary outputs. 4. device is static and should operate below 1 hz, but is only tested down to 4 mhz with the pll enabled. with the pll bypassed, the device is only tested down to 8mhz. 5. maximum i ol or i oh currents per pin will be characterized and published at a later date. target values are 10 ma. 6. typicals are based on a limited number of samples and are not guaranteed. the values listed are at room temperature and v ref = v cc = 5.5v. 7. v ih max for port 0 is v ref + 0.5v. 8. this specification is not tested in production and is based upon theoretical estimates and/or product characterization.
17 automotive ? pr oduct preview 5.2 ac characteristics (over specified operating conditi ons) test conditions: capacitive load on all pins = 100 pf, rise and fall times = 10 ns, f xtal 1 = 8mhz with pll enabled in clock-doubler mode. table 7. ac characteristics symbol parameter min max units the 87c196lb will meet these specifications f xtal 1 frequency on xtal1, pll in 1x mode 8.0 20.0 mhz (1) frequency on xtal1, pll in 2x mode 4.0 10.0 f operating frequency, f = f xtal 1 ; pll in 1x mode 8.0 20.0 mhz operating frequency, f = 2f xtal 1 ; pll in 2x mode t period t = 1/f 50 125 ns t xhch xtal1 high to clkout high or low 20 110 ns (2) t clcl clkout cycle time 2t ns t chcl clkout high period t C 10 t + 15 ns t cllh clkout falling to ale rising C 10 15 ns t llch ale falling to clkout rising C 20 15 ns t lhlh ale cycle time 4t ns t lhll ale high period t C 10 t + 10 ns t avll address setup to ale low t C 15 ns t llax address hold after ale low t C 40 ns t llrl ale low to rd# low t C 30 ns t rlcl rd# low to clkout low 4 30 ns t rlrh rd# low to rd# high t C 5 ns t rhlh rd# high to ale rising t t + 25 ns (3) t rlaz rd# low to address float 5 ns t llwl ale low to wr# low t C 10 ns t clwl clkout low to wr# falling edge C 5 25 ns t qvwh data valid to wr# high t C 23 ns t chwh clkout high to wr# rising edge C 10 15 ns t wlwh wr# low to wr# high t C 20 ns t whqx data hold after wr# high t C 25 ns notes: 1. testing performed at 4.0 mhz with pll enabled. with the pll bypassed, the device is only tested down to 8 mhz. however, the device is static by design and will typically operate below 1 hz. 2. typical specifications, not guaranteed. 3. assuming back-to-back bus cycles. 4. 8-bit bus only.
pr oduct preview 18 automotive ? t whlh wr# high to ale high t C 10 t + 15 ns (3) t whax ad15:8 hold after wr# high t C 30 (4) ns t rhax ad15:8 hold after rd# high t C 30 (4) ns the system must meet these specifications to work with the 87c196lb t avdv address valid to input data valid 3t C 55 ns t rldv rd# low to input data valid t C 22 ns t cldv clkout low to input data valid t C 50 ns t rhdz rd# high to input data float t ns t rxdx data hold after rd# inactive 0 ns table 7. ac characteristics (continued) symbol parameter min max units notes: 1. testing performed at 4.0 mhz with pll enabled. with the pll bypassed, the device is only tested down to 8 mhz. however, the device is static by design and will typically operate below 1 hz. 2. typical specifications, not guaranteed. 3. assuming back-to-back bus cycles. 4. 8-bit bus only.
19 automotive ? pr oduct preview 6.0 thermal characteristics all thermal impedance data is approximate for static air conditions at 1 watt of power dissipation. values will change depending on operating conditions and the application. the intel packaging handbook (order number 240800) describes intels thermal impedance test methodology. the components quality and reliability handbook (order number 210997) provides quality and reliability information. 7.0 design considerations to be supplied. 8.0 device errata there is no known device errata at this time. 9.0 datasheet revision history this datasheet is valid for devices with an a at the end of the topside field process order (fpo) number. datasheets are changed as new device information becomes available. verify with your local intel sales office that you have the latest version before finalizing a design or ordering devices. table 8. thermal characteristics package type q ja q jc AN87C196LB (52-pin plcc) 42 c/w 15 c/w notes: 1. q ja = thermal resistance between junction and the surrounding environment (ambient). measure- ments are taken 1 ft. away from case in static air flow environment. q jc = thermal resistance between juction and package surface (case). 2. all values of q ja and q jc may fluctuate depending on the environment (with or without airflow, and how much airflow) and device power dissipation at temperature of operation. typical variations are 2 c/w. 3. values listed are at a maximum power dissipation of 0.50 w.

▲Up To Search▲

Price & Availability of AN87C196LB

	To Download AN87C196LB Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .